High voltage half bridge circuits can be configured to drive switched voltages to a load (e.g., to an electric motor) that take on voltage values including a high voltage (e.g., six hundred volts) and a low voltage (e.g., a ground voltage). The high voltage half bridge circuits described herein operate nonlinearly providing only the high voltage to the load at some times and the low voltage to the load at other times. In some applications, by changing a duty cycle of the high voltage applied to the load, the power to the load can be changed, resulting, for example, in changes to a speed of rotation of an electric motor load.
Half bridge circuits comprise a series coupling of two transistors. A node coupling the two transistors is coupled to the load. In order to control the half bridge, a control circuit is coupled to control nodes (e.g., gates) of the two transistors.
High voltage, solid state, half bridge circuits are most often constructed with two NMOS field effect transistors (FETS) or two NPN insulated gate bipolar transistors (IGBTs) coupled in series to form the half bridge. The high side NPN power transistor, i.e., the NPN power transistor coupled to the high voltage, requires a control voltage at its base that can take on voltage values from the negative supply voltage (usually ground) when the high side transistor is off to a voltage higher than the high supply voltage (e.g., higher than about six hundred volts) when the high side transistor is on. In order to achieve this wide range of control voltages, the control circuit requires a high voltage level translator (or level shifter).
One exemplary level shifter is described in U.S. Pat. No. 5,917,359, issued Jun. 29, 1999. Some elements of the level shifter described in U.S. Pat. No. 5,917,359 have become common.
Referring now to FIG. 1, a half bridge 19 is comprised of two NPN power IGBTs (insulated gate bipolar transistors) 17, 18, coupled together at a node HS. The node HS is coupled to a load 21, e.g., to an electric motor. The transistor 17 is a high side transistor coupled to a high voltage power supply, VDD. The power supply. VDD, can have a voltage of hundreds of volts, for example, six hundred volts. The transistor 18 is a low side transistor coupled to a lower voltage, e.g., to a ground voltage.
A control circuit includes a conventional high voltage control circuit 10 (a level shift circuit) coupled to control the high side transistor 17 and a low voltage control circuit 30 coupled to control the low side transistor 18. The high voltage control circuit 10 and the low voltage control circuit 30 can be integrated onto a common substrate. In some embodiments, the half bridge, circuit 19 is separate from the common substrate.
The high voltage control circuit 10 can include a pulse generating circuit 1 coupled to receive an input signal and configured to generate on and off signals (pulse signals), preferably having opposite states. The high voltage control circuit 10 can also include two high voltage FETs 2, 3 coupled to receive the on and off pulse signals at control inputs (e.g., gates), two resistors 4, 5 coupled to drains of the two FETs 2, 3, two CMOS inverters 6, 7 also coupled to the drains of the FETs 2, 3, a protection circuit 27 coupled to the two inverters 6, 7, a latch 15 coupled to the protection circuit 27, a buffer circuit 11, 12, 13, and a capacitor 16 coupled at one end to the node, HS, and coupled at the other end to provide a voltage VB (a bootstrap supply) as a power supply to portions of the high voltage control circuit 10.
The capacitor 16, which is referred to herein as a “bootstrap capacitor,” can be supplemented in parallel with a larger off-chip capacitor. CMOS logic 6, 7, 27, 15, 11 operates across the bootstrap supply provided by the capacitor 16, i.e., across the voltage VB and a voltage at the node HS. The voltage difference between the voltage VB and the voltage at the node HS can be maintained at a low voltage, for example, fifteen volts, though both the voltage VB and the voltage at the node HS can move together through a wide range of voltages.
The high voltage control circuit 10 can also include a diode D10 and a resistor R10 coupled in series to receive a power supply voltage Vcc, which can, for example, be about fifteen volts.
A capacitor 20 can be coupled between the high voltage power supply VDD and ground.
Assume that the high voltage supply VDD is set to six hundred volts and the power supply voltage VCC, is set to fifteen volts. When the transistor 18 is on, the node HS has a voltage near ground, and the bootstrap capacitor 16 charges to within one diode voltage of the power supply voltage VCC, or approximately 14.3 volts. As the half bridge circuit 19 is toggled, voltage at the node HS toggles between zero volts and six hundred volts, and the voltage at the far end of the capacitor 16 moves accordingly. Thus, the difference between the voltage VB and voltage at the node HS (the bootstrap supply voltage) remains nearly constant at 14.3 V. Therefore, the CMOS circuitry 6, 7, 27, 15, 11 need only tolerate a fifteen volt supply, but the CMOS circuitry 6, 7, 27, 15, 11 must be sufficiently isolated from ground to tolerate six hundred fifteen volts, and FETs 2 and 3 must tolerate six hundred fifteen volts.
In operation, parasitic capacitances of the high voltage FETS 2 and 3 present a problem common to all such high voltage control circuits (i.e., level translator circuits or level shift circuits). In essence, the parasitic capacitances must be charged and discharged during high voltage switching. When the high side transistor 17 is abruptly turned on (and the low side transistor 18 is abruptly turned off), the drain capacitance of the FETS 2 and 3 is charged to a high voltage through the resistors 4, 5, creating transient voltage drops across both of the resistors 4, 5 at the same time (i.e., a common-mode voltage transient). Such transients could be detected by the CMOS logic controlling the high side transistor 17, leading to erroneous control of the half bridge 19 and potential destruction of one of the transistors 17, 18 due to high current spikes though both of the transistors 17, 18 at the same time. This problem can be partially solved by the protection circuit 27, which prevents changes to the state of the set-reset latch 15 whenever both inverters 6 and 7 present transients at the same time (due to the above-described common mode transient).
While the protection circuit 27 can provide some protect from common mode transient voltages, the protection circuit also tends to slow down the high voltage control circuit 10, resulting in a limit on the rate at which the half-bridge 19 can be switched.
Therefore, it would be desirable to provide a high side control circuit and associated technique that can provide proper control of a half bridge, reducing or eliminating the effect of common mode voltage transients, but without limiting a speed at which the half bridge can be switched.